1. Field of the Invention
The present invention relates to a momentary-disconnection-free switching device for a signal in an optical synchronous communicating device.
2. Description of the Related Art
The following description is provided by assuming SONET, but a person skilled in the art should easily understand that the description is similarly applicable to SDH.
There is a problem that a momentary disconnection of a signal occurs when switching is made between active and standby devices of Switch Fabrics (VT Switch Fabrics) which crossconnect a VT (Virtual Tributary) signal mapped in an STS-1 payload in a SONET equipment.
FIG. 1 shows the structure of an STS-1 frame in a SONET system. A schematic in the top stage of FIG. 1 represents the STS-1 frame, which is composed of a transport overhead (TOH) and a payload. H1 and H2 bytes of the transport overhead are pointers which indicate a position where data within the payload starts, and H3 is a stuff byte used when negative stuffing is made. A J1 byte indicates the starting position of the payload, and data of a predetermined length, which succeeds the J1 byte, is payload data. As shown in this figure, the payload does not always start at the beginning of the payload of the STS-1 frame, and is designed to start at an arbitrary position. Therefore, the starting position of the payload is indicated by the H1 and H2 bytes.
A schematic shown in the middle stage of FIG. 1 shows the structure of the payload of the STS-1 frame. In the STS-1 payload, VT signals are mapped by 28 channels from a channel 1 to a channel 28. For each of the VT signals, one VT frame is configured by 4 STS-1 frames. In each of the STS-1 frames, a path overhead (POH) is provided, and VT signals having V1 to V4 bytes as a head are subsequently mapped.
A schematic shown in the bottom stage of FIG. 1 shows the structure of a VT frame. The VT frame has V1 to V4 bytes as a header, and the payload of the VT frame starts at a V5 byte. Also the starting position of the VT payload which starts at the V5 byte is not predetermined but starts at an arbitrary position. Accordingly, a pointer which indicates the starting position of the V5 byte is set in the V1 and V2 bytes.
As described above, VT signals of 28 channels are mapped per STS-1. Each of the VT signals is composed of 4 multi-frames, and its Flag (00h to 03h) is buried in an H4 byte. The VT frame is configured by 108 bytes obtained by multiplying 27 and 4, and the V1 and V2 bytes are pointer bytes which indicate the position of the V5 byte, the beginning of the VT payload.
FIGS. 2A and 2B explain a VT pointer.
Referring to FIG. 2A, V1 and V2 bytes are composed of NDF bits, SS bits, and a “10”-bit pointer. A V3 byte is composed of a deletion bit for making negative stuffing and an addition bit for making positive stuffing. The V3 byte accommodates the data of the payload at the time of negative stuffing. Referring to FIG. 2B, for a time series data sequence when a VT frame is transmitted, the V1 byte is initially transmitted, and the data of the payload is transmitted thereafter. Data next to the V1 byte is the payload data the pointer value of which is 78. Thereafter, payload data the pointer values of which are up to 103 succeed. Next, the V2 byte is transmitted. Data next to the V2 byte is payload data the pointer value of which is 0. Thereafter, data the pointers values of which are up to 25 succeed. Then, the V3 byte is transmitted. The V3 byte is a stuff byte. The number of bits of the V3 byte is decreased when negative stuffing is made, whereas the number of bits of the V3 byte is increased when positive stuffing is made. The V3 byte is a negative stuff byte, and copes with an increase/decrease in a pointer value by accommodating a portion of data of the payload in the V3 byte when negative stuffing is made, or by unaccommodating data in a byte next to the V3 byte when positive stuffing is made. Payload data the pointer values of which are from 26 to 51 succeed the V3 byte. Next, a V4 byte succeeds, and payload data the pointer values of which are 52 to 77 succeed the V4 byte.
Conventionally adopted is a method for arranging a pointer circuit in a stage preceding a crossconnect circuit in order to effectively configure the scale of the crossconnect circuit for the crossconnection of a VT signal (see Patent Document 1).
In a SONET transmitting device, a VT Switch Fabric (VTSF) is formed to be able to be mounted/unmounted in accordance with Network Application on a user side, and Switch Fabric mounted with a pointer circuit and a crossconnect circuit are popularized.
FIG. 3 shows Switch Fabrics each of which is mounted with a VT pointer circuit and a crossconnect circuit.
An STS signal input to an interface 10 undergoes a pointer process of an STS signal level in an STS pointer circuit 11. Interfaces 10 are provided by a number that can accommodate the lines of STS-SFs (Switch Fabrics) 12 and 13. Also STS pointer circuits are provided by the same number. The STS-SFs 12 and 13 have a redundant configuration of active and standby. An STS-1 signal selected by the STS-SF 12 is input to a VT-SF (Switch Fabric) 14. STS-1 signals from both of the active and the standby fabrics are selected by selectors 16 and 19. Then, a VT pointer process is performed in VT pointer circuits 17 and 20, and a crossconnect process is performed in VT crossconnect circuits 18 and 21. The signal for which the VT crossconnect process is performed is fed back to the STS-SFs 12 and 13 via selectors 22 and 23, and input to an interface 24 via a selector 25 for switching between active and standby. Then, the STS-1 signal after the crossconnect process is performed is output from the interface 24. If VT crossconnect is not required, the VT-SFs 14 and 15 can be unmounted.
In the meantime, with the advance of device technology and with a growing demand of a network, the line processing capacity of a VT Switch Fabric increases, and an influence exerted by a momentary disconnection of a line, which occurs when switching is made between active and standby circuits of Switch Fabrics at the time of maintenance, has become unignorable, leading to a vital demand for the necessity of momentary-disconnection-free switching.
To resolve this, a technique for arranging a VT pointer circuit in an interface unit of a SONET transmitting device is sometimes adopted. In this case, however, a VT pointer circuit is always mounted even when VT Switch Fabric is not used, which is not economic.
FIG. 4 shows Switch Fabric having a configuration where a VT pointer circuit is provided within an interface device. In this figure, the same constituent elements as those shown in FIG. 3 are denoted with the same reference numerals of FIG. 3, and their explanations are omitted.
In FIG. 4, VT pointer circuits are removed from VT-SFs 14a and 15a. Alternatively, a VT pointer circuit 30 is provided within an interface 10a. A signal for which a pointer process is performed by an STS pointer circuit 11, and a signal for which a pointer process is performed by the VT pointer circuit 30 are selectively output by a selector 31.
FIG. 4 shows one example where momentary-disconnect-free switching of VT-SF is made. Namely, the VT pointer circuit is arranged in the interface 10a. In this case, a VT pointer is processed in the interface 10a, and its signal is branched by STS-SFs 12 and 13. Therefore, pointer values that indicate the starting position of VT payload data always become the same value in both active and standby VT-SFs 14a and 15a, whereby momentary-disconnection-free switching can be made. However, a VT pointer circuit must be arranged in all cases even if a VT line is not processed. As a result, the scale of the circuit of the entire device and its cost increase.
Accordingly, expectations that momentary-disconnection-free switching is made with VT Switch Fabric mounted with a pointer circuit as conventional are raised.
[Patent Document 1] Japanese Patent Application Publication No. 2003-101501
There is a case where different pointer values are inserted and output on active and standby sides when a pointer process is performed in VT Switch Fabrics which are redundantly arranged within a device. Three factors exist as a cause of this case.
FIG. 5 shows the fundamental configuration of a VT pointer circuit.
The VT pointer circuit is configured by a memory 35, a WR (Write) address counter 37, an RD (Read) address counter 38, and a phase comparator 36. The WR address counter 37 counts write addresses from 0 to 7 according to an enable signal which is synchronous with write data (WR data). The write data is written to an address output from the WR address counter 37 of the memory 35. The RD address counter 38 is a counter for issuing an instruction to read from which address of the memory 35 data is to be read. Also this counter counts read addresses from 0 to 7 according to an enable signal. The phase comparator 36 detects a difference between the address values of the WR address counter 37 and the RD address counter 38, and controls the RD address counter 38 in order to keep the difference to be a definite value.
In the memory 35, addresses from 0 to 7 are defined, data write and read to/from the memory 35 are performed based on the address counters both on WR (write) and RD (read) sides. To prevent the data write and read operations from conflicting with, the phase comparator 36 for obtaining a phase difference value is arranged. If the phase difference value enters an INC/DEC region (a window indicating a difference value of phases in order to determine whether or not to perform a stuff process), a pointer value of a pointer inserting unit (not shown) is updated, and negative stuffing and positive stuffing are made to move a phase difference between the data write and read to/from the memory 35 to a normal operation region. As a result, a signal can be communicated without losing data.
The initial state of the phase comparator 36 starts at a difference value of 4 as a result of a comparison made between respective counter values. However, the difference decreases or increases with fluctuations in the phase on the WR side. In the configuration of the pointer circuit shown in FIG. 5, three addresses such as 3, 4, and 5 exist in the normal region, but gaps of OH (V1 to V4) exist for a VT payload signal. Therefore, a phase comparison result becomes a pattern which repeats 3<->4 or 4<->5.
In FIG. 5, portions of the WR address, which are enclosed with thick lines, are INC and DEC regions.
FIGS. 6 and 7 explain operations performed when an OH gap occurs with reference to power-up time.
As described by referring to FIG. 5, the WR address counter 37 and the RD address counter 38 run when an enable signal is input. Accordingly, if the enable signal does not exist, namely, if data conflicts with the timing of an overhead (OH) (conflicts with the timings of the V1 to V4 bytes), the counting of the counter values stops. The state where the counting stops is referred to as an occurrence of a gap. Therefore, a phase difference between the write and the read sides changes with the timing when the counting stops on the write and the read sides.
FIG. 6 shows a case where an OH gap initially occurs on the write side, whereas FIG. 7 shows a case where an OH gap initially occurs on the read side.
In FIG. 6, in the initial state, WR addresses of WR data are counted from 0 to 7, and the counting of RD addresses of RD data starts when the WR address is 4 (1). Accordingly, a phase comparison result PC becomes 4 at this time. When any of the V1 to V4 bytes is input on the WR data side (represented as “v” in FIG. 6), a gap occurs and the WR address counter once stops. Therefore, the counting of the WR addresses delays by 1. However, since a gap has not occurred yet in the RD data, the RD address counter continues to count. Accordingly, an RD address becomes 0 when the WR address is 3, and the phase comparison result PC becomes 3 (2). Next, when a gap occurs on the RD data side, the RD address counter once stops and the counting of the RD addresses delays by 1. As a result, restoration is made to the initial state where the RD address is 0 when the WR address is 4 (3). Accordingly, if a gap occurs on the write side first, the phase comparison result comes and goes between 3 and 4.
In FIG. 7, in the initial state, the WR addresses of WR data are counted from 0 to 7, and the counting of the RD addresses of RD data starts when the WR address is 4 (1). Accordingly, the phase comparison result PC becomes 4 at this time. When any of the bytes of V1 to V4 appears on the RD data side (represented as “v” in FIG. 7), a gap occurs and the RD address counter once stops. Therefore, the counting of the RD addresses delays by 1. However, a gap has not occurred yet in the WR data, the WR address counter continues to count. Accordingly, the RD address becomes 0 when the WR address is 5, and the phase comparison result PC becomes 5 (2). Next, when a gap occurs on the WR data side, the WR address counter once stops, and the counting of WR addresses delays by 1. As a result, restoration is made to the initial state where the RD address is 0 when the WR address is 4 (3). Accordingly, if a gap occurs on the read side first, the phase comparison result comes and goes between 5 and 4.
As described above, if the pointer circuit is set so that the phase difference at the time of power-up is initialized to be a position of 4, it runs between 3<->4 if a gap occurs on the WR side first, or runs between 4<->5 if a gap occurs on the RD side first.
In the same devices, no constraints are imposed on times at which active and standby devices are mounted, and accordingly, timings when the active and the standby pointer circuits are powered up are completely independent. Therefore, either of the active and the standby pointer circuits can possibly run between 3<->4 in the normal region of the pointer unit, whereas the other can possibly run between 4<->5 due to the relationship between the timings of power-up of the active and the standby pointer circuits when being mounted.
As described above, if a pointer value is updated as a result of a phase difference which enters an INC region or a DEC region only on the write side of the active and the standby sides, stuffing occurs and the pointer value is newly updated, leading to a difference between the pointer values of the active and the standby sides.
FIGS. 8 and 9 explain a problem posed when the active and the standby sides run in different phases.
FIG. 8 shows an example where Increment instruction reaches the write side and RD-INC (increment) occurs only in an active side VTSF, whereas FIG. 9 shows an example where Decrement instruction reaches the write side, and an RD-DEC (Decrement) occurs only in a standby side VTSF.
In FIG. 8, assume that the active side VTSF runs so that a phase difference between WR and RD addresses comes and goes between 3 and 4, and the standby side VTSF runs so that the phase difference between WR and RD addresses comes and goes between 4 and 5. In this case, if the increment instruction reaches the write side, the phase difference between WR and RD addresses comes and goes between 3 and 4 in the standby side VTSF. In the meantime, the phase difference between WR and RD addresses comes and goes between 2 and 3 in the active side VTSF. However, if the phase difference becomes 2, it enters the INC region. Therefore, an operation for incrementing the read side address counter is performed. Namely, stuffing occurs, which leads to a change in the pointer value. In this way, the pointer values of the active and the standby sides change.
In FIG. 9, assume that the active side VTFS-SF runs so that the phase difference between WR and RD addresses comes and goes between 3 and 4, whereas the standby side VTSF runs so that the phase difference between WR and RD addresses comes and goes between 4 and 5. If the decrement instruction reaches the write side, the phase difference between WR and RD addresses comes and goes between 4 and 5 in the active side VTSF. In the meantime, the phase difference between WR and RD addresses comes and goes between 5 and 6 in the standby side VTSF. However, if the phase difference becomes 6, it enters the DEC region. Therefore, an operation for decrementing the read side address counter is performed. Namely, stuffing occurs, which leads to a change in the pointer value. In this way, the pointer values of the active and the standby sides change.
FIG. 10 explains the second factor which makes the pointer values of the active and the standby sides different.
The pointer circuit makes a comparison between WR and RD addresses in order to prevent the phases of the write (WR) and the read (RD) sides from conflicting with, performs a pointer process when the phase difference enters a predetermined INC region or DEC region, and performs an operation for restoring the phase difference to a normal region. Data which reaches the WR side is data transferred from STS Switch Fabric. The phase on the WR side can possibly shift on the active and the standby sides due to a delay difference of wiring or a device. The shift of the phase on the WR side can possibly make the times of reaching the INC or DEC region different, which makes the pointer values of the active and the standby sides different.
Assume that DATA 1 having a delay time of ΔT1 is input to the VT pointer circuit of the active side VTSF, whereas DATA 2 having a delay time of ΔT2 is input to the VT pointer circuit of the standby side VTSF as shown in FIG. 10. If the values of ΔT1 and ΔT2 differ, a difference arises in the phases of DATA 1 and DATA 2. This leads to a difference between the pointer processes of the VT pointer circuits on the active and the standby sides. As a result, pointer values differ on the active and the standby sides.
FIGS. 11 and 12 explain the third factor which makes the pointer values of the active and the standby sides different.
An 8-kHz timing pulse is distributed from STS switch Fabric to each interface in order to implement a crossconnection in the STS Switch Fabric in a SONET equipment. Since the VT frame structure is a 2-kHz multi-frame structure in a VT pointer circuit in the VT Switch Fabric, a 2-kHz timing pulse is generated from the 8-kHz timing pulse. Because the references of starting the generation of the 2-kHz timing pulse are mutually independent on the active and the standby sides at this time, starting positions may sometimes differ. Therefore, the timing of data read from the memory in the VT pointer circuit does not become the same as the timing of the transmitting side, which makes the pointer values different.
If the 2-kHz timing pulse is generated from the 8-kHz timing pulse, a ¼ divider is used. At this time, the timing of starting to divide a cycle shifts, thereby generating three types of 2-kHz timing as shown in FIG. 12. If this shift occurs between the active and the standby sides, a difference arises in time distance to the timing of a V5 byte with regard to the 2-kHz timing pulse although the input timings of a V5 byte are the same.
Due to these three factors, a suddenly changed pointer value is fed to a device in a succeeding stage when switching is made from the active side Switch Fabric to the standby side VT Switch Fabric. Normally, a pointer receiving circuit is manufactured in compliance with Pointer Action Rule stipulated in GR-253-CORE of Telcordia. Therefore, an ACT-pointer value (a value that a receiving pointer circuit recognizes as a reception pointer value) is configured not to follow such a sudden change in a pointer value.
FIGS. 13 to 15 explain an operation for changing an ACT-Pointer value.
FIGS. 13 to 15 show Rules for changing a pointer value. The pointer value is changed in an NDF (New Data Flag) state (FIG. 13), or with Stuff control performed by inverting I and D bits (FIGS. 14 and 15). If a difference exists between the pointer values of the active and the standby sides due to the above described factors, conditions shown in FIGS. 13 to 15 cannot be satisfied if switching occurs between the active and the standby sides, and a SONET equipment in the succeeding stage cannot follow a sudden change in the pointer value for a certain time period, leading to an occurrence of a line error.
Accordingly, a VT payload error (line hit) will occur until the SONET device in the succeeding stage again follows the sudden change in the pointer value, which is caused by switching from the active side to the standby side.